1. Field of the Invention
This invention relates generally to electronic circuits and, more particularly, to logic circuits that generate signals in response to coincident edges of processor clock signals and bus clock signals. A data processing system typically includes a single bus clock controlling activity on the system bus and multiple processor clocks controlling internal activity in the processor components. In order to coordinate certain intercomponent activity, such as the transfer of data, the processor clocks must be synchronized with the bus clock. This synchronization is typically coordinated by the generation of a signal in the processor component identifying the coincidence of the leading edges (illustrated by rising edges herein) of the bus clock signal and the processor clock signal.
2. Description of the Related Art
In computer systems, the clock controlling the operation of the processor typically has a far higher frequency than the clock that is applied to the processing system bus. For example, in personal computer systems (PCs or Pentium.TM.-compatible processor systems), the processor clock normally generates a clock signal with at least twice the frequency of the bus clock signal. As newer generations of processors become available for personal computing systems, the frequency of the processor clocks tend to exceed the bus clock frequencies by increasingly wide margins. In order to facilitate compatibility between the processor operating frequency and the bus operating frequency, processors are designed such that ratio of the processor clock frequency to the bus clock frequency is a whole integer or a half integer. Table 1 provides typical examples of the processor clock frequency compared to the bus clock frequency.
TABLE 1 RATIO OF THE PROCESSOR CLOCK FREQUENCY TO THE BUS CLOCK FREQUENCY Processor Clock Bus Clock Frequency Frequency Ratio 133 MHz 66 MHz 2 200 MHz 66 MHz 3 233 MHz 66 MHz 3.5 266 MHz 66 MHz 4 300 MHz 66 MHz 4.5
Processors frequently include synchronization circuitry, such as phase-locked loops, for establishing a timing relationship between processor clock frequency and the bus clock frequency. Consequently, when the processor clock frequency to bus clock frequency ratio is a whole integer, each rising edge of the bus clock signal B.sub.CLK is coincident with a rising edge of the processor clock signal P.sub.CLK. Referring to FIG. 1A, a coincidence circuit 10 for providing the EVENB.sub.CLK signal, the signal designating the coincidence between the P.sub.CLK signal and the B.sub.CLK signal, according to the prior art, is shown. The coincidence circuit 10 includes a flip-flop unit 11 that has P.sub.CLK signal applied to the D terminal. The B.sub.CLK signal is applied to the clock terminal of flip-flop 11. The Q terminal of the flip-flop unit 11 is coupled to the D terminal of flip-flop unit 12 and to a first terminal of logic AND gate 13. The flip-flop unit 12 has the P.sub.CLK signals applied to the clock terminal. The Q terminal of flip-flop 12 is coupled to a second, inverting terminal of logic AND gate 13 and is coupled to a reset terminal of flip-flop unit 11. The output terminal of logic AND gate 13 is coupled to latch unit 14. The output signal of latch unit 14 is the P.sub.CLK -B.sub.CLK leading edge coincident signal EVENB.sub.CLK. The operation of the coincidence circuit can be understood with reference to FIG. 1B. In FIG. 1B, the relationship of the B.sub.CLK signal, the P.sub.CLK signal, and the EVENB.sub.CLK signal are shown for the configuration wherein the frequency of the P.sub.CLK signal is 3.times. the frequency of the B.sub.CLK signal. The dotted lines indicate the actual coincidence of the B.sub.CLK and the P.sub.CLK signals. The leading edge of the EVENB.sub.CLK signal is delayed half P.sub.CLK signal cycle and has a signal width of one P.sub.CLK signal cycle. As will be clear, this circuit relies on the alignment of the B.sub.CLK and the P.sub.CLK signal for proper operation. As a practical matter, the circuits that provide these signals are sensitive to noise and to component parameters that prevent the attainment of idealized waveforms. These factors can provide a phase shift in the processing system signals, the phase shift providing uncertainty with respect to the relationship of the leading edges of the signals. Referring to FIG. 2, the effect of these factors on the leading edge of the P signal is shown. The uncertainty in the leading edge of the P.sub.CLK signal as compared to the B.sub.CLK signal is shown by the shaded area in the P.sub.CLK signal and is designated as .+-..DELTA.. In addition, when the P.sub.CLK frequency is very much greater than the B.sub.CLK signal frequency, the half cycle time of P.sub.CLK signal can approach the magnitude of the phase error .DELTA. and result in a lack of ability to generate accurately the EVENB.sub.CLK signal. An example of this difficulty is illustrated in FIG. 3. The leading edge of the B.sub.CLK signal leads the P.sub.CLK signal by a sufficient time that the flip-flop unit 11 of FIG. 1 is unable to sample properly the P.sub.CLK signal. At low P.sub.CLK frequencies, the inability to generate the EVENB.sub.CLK signal is less likely to occur because the P.sub.CLK cycle time is long enough to compensate for a relative phase shift between the B.sub.CLK signal and the P.sub.CLK signal. At high frequencies, the circuit is more prone to failure because the skew between the signals will remain fixed (in the best situation) as the P.sub.CLK cycle will become smaller.
In addition, when the processor clock signal frequency to bus clock signal frequency ratio is a half integer, then the alternating rising signal edges (such as even leading signal edges) of the bus clock signal are coincident with leading edges of the processor clock signal, and the remaining signal rising edges (such as the odd signal leading edges) of the bus clock signal are not coincident with signal rising edges of the processor clock signal.